Every radio that converts an RF signal to digits crosses the same fundamental boundary: the analogue-to-digital converter. The architecture chosen for that converter — and the compromises it imposes on speed, resolution, power, and cost — has defined what was possible in wireless design across every generation of the technology. The story of the Analog Devices AD936x series cannot be separated from the forty-year evolution of ADC design that made it possible. Understanding that lineage explains not only what the chip achieved, but why it arrived when it did and why no equivalent product existed ten years earlier.
Flash and Pipeline — The First Digital Radio Era
The earliest high-speed ADC architecture is the flash converter: a bank of 2N comparators operating in parallel, each referencing a different voltage tap on a resistor ladder. Every comparator fires simultaneously, the thermometer code is encoded, and a result is available in a single clock cycle. Flash converters are extraordinarily fast — multi-GHz sample rates have been demonstrated — but the comparator count doubles for every additional bit of resolution, making anything beyond 8 bits prohibitively power-hungry and silicon-expensive. Early digital radar and oscilloscope systems used flash ADCs for exactly this reason: they needed speed far more than they needed dynamic range.
The pipeline ADC extended the achievable resolution by splitting the conversion across multiple stages, each resolving a few bits before amplifying the residue and passing it to the next stage. A 14-bit pipeline ADC might use seven stages of 2 bits each, plus correction logic — a practical architecture that reached 12–16 bits at hundreds of megasamples per second by the mid-1990s. This is the ADC architecture that enabled the first generation of software-defined radio in its recognisable form: the receiver chain was still dominated by analogue components — low-noise amplifier, mixer, intermediate-frequency filter — but the ADC sat at the IF output and digitised a relatively narrow slice of spectrum, which DSP hardware then processed. The antenna was analogue; the intelligence was increasingly digital. It was a beginning, not a solution.
SAR and Sigma-Delta — Resolution and the Noise-Shaping Revolution
The successive-approximation register (SAR) ADC takes a different approach: it performs a binary search through the input range, testing one bit per clock cycle from most-significant to least-significant. The result is an architecture that achieves 12–18 bits of resolution with very low power consumption, making it the dominant choice for measurement instrumentation, sensor interfaces, and any application where moderate speed and excellent precision matter more than raw throughput. SAR ADCs are not fast enough to sit at RF or even at a wide IF, but they became the workhorse of the baseband world — precision measurement of signals that had already been moved to low frequency by an analogue front end.
The sigma-delta ADC introduced a fundamentally different principle. Rather than resolving every input sample to full precision, a sigma-delta modulator deliberately oversamples at a high clock rate — many times the Nyquist rate — using a coarse internal quantiser (sometimes a single comparator) inside a feedback loop. The feedback shapes the quantisation noise so that it is pushed out of the signal band and into higher frequencies, where it can be removed by a digital decimation filter. The net result is extraordinary in-band resolution: 20–24 bits in audio converters became routine. More significantly, the noise-shaping principle demonstrated a general truth: in ADC design, clock speed and amplitude resolution can be traded against each other, and as CMOS process nodes shrink and transistors become faster and cheaper, that trade becomes continuously more favourable. This insight planted the intellectual seeds of what would eventually become direct RF digitisation.
The VCO ADC — A Different Path to the RF Frontier
A voltage-controlled oscillator used as an ADC input stage offers something architecturally attractive: the VCO converts an input voltage to a frequency, and counting oscillator cycles over a fixed window produces a digital output whose value is proportional to the input — with first-order noise shaping arising naturally from the counting process, without any explicit feedback path. VCO-based ADC designs have been demonstrated at multi-GHz clock rates in advanced CMOS nodes, and because VCO frequency scales favourably with process shrinkage, the architecture improves with each technology generation in a way that comparator-heavy flash designs do not. Research groups at MIT, Stanford, and KU Leuven have published VCO ADC implementations targeting direct RF sampling at L-band and S-band frequencies. The architecture has not yet displaced pipeline converters in production RF silicon, but it represents an active and credible research direction toward the long-standing goal of placing the ADC directly at the antenna — eliminating the downconversion chain entirely.
The Quadrature Pair and Direct Conversion — The Architecture the AD936x Made Real
The architectural step that made the AD936x possible was not a new ADC topology but a different placement of a proven one. In a direct-conversion (zero-IF, homodyne) receiver, the local oscillator is tuned directly to the carrier frequency rather than to an intermediate frequency. The RF signal is mixed simultaneously with the LO and with a 90-degree-shifted copy of the LO, producing two baseband output channels: the in-phase (I) component and the quadrature (Q) component. Together these two channels carry the complete complex amplitude of the received signal at a frequency of zero hertz — the original RF spectrum folded down to DC. Two relatively slow, high-resolution ADCs can then digitise the I and Q channels, and all further processing is done in the digital domain.
The approach had been known since the superheterodyne era, but practical implementation was severely complicated by analogue imperfections: DC offset caused by local oscillator leakage into the mixer, gain and phase imbalance between the I and Q paths, and flicker noise from MOSFET devices concentrated exactly at DC where the wanted signal now lived. These were not theoretical problems — they corrupted the signal and limited the dynamic range. Solving them required embedding DC offset correction loops, I/Q calibration engines, and flicker noise compensation circuits into the silicon itself, running continuously to track temperature and supply variations. When CMOS mixed-signal process technology matured to the point where all of this correction could be implemented reliably at volume at an acceptable die cost, the integrated direct-conversion transceiver became manufacturable. That point arrived around 2013.
The AD936x Era — A Price-Capability Cliff
The Analog Devices AD9361 was not the first integrated direct-conversion RF transceiver, but it was the first to reach a price-performance intersection that broke the market open. Covering 70 MHz to 6 GHz with up to 56 MHz channel bandwidth, a 2×2 MIMO architecture, and a fully programmable analogue and digital signal path — all behind a single SPI control interface — it condensed what had previously required a rack of equipment into a chip that cost under $40 in volume. Ettus Research placed the AD9361 inside its USRP B200 and B210, extending the reach of a professional research platform. Analog Devices then packaged the closely related AD9363 inside the ADALM-PLUTO Active Learning Module and sold it for $200 — a full-duplex transceiver spanning most of the radio spectrum, available to any university student on the planet.
The price collapse was not merely a procurement convenience. It changed the culture of RF research. Labs that had shared one or two USRP units could instrument every workbench. Defence contractors could deploy expendable sensor nodes. Amateur experimenters could transmit, not just receive. The QO-100 / Es’hail-2 geostationary amateur transponder — 2.4 GHz uplink, 10.489 GHz downlink — was activated in 2019, and the PlutoSDR became its dominant ground station transceiver almost immediately; thousands of operators across Australia, New Zealand, Europe, and the Middle East now access it daily on $200 hardware. Open cellular networking followed: srsRAN and OpenAirInterface, the two leading open-source 4G/5G stack implementations, support AD9361-class hardware natively, meaning a complete 5G NR base station can be deployed from a PlutoSDR-class board for research purposes. Maia SDR, a fully open-source Rust-and-FPGA firmware for the Pluto written by Daniel Estévez (EA4GPZ), delivers a 61 Msps wideband browser-based spectrometer from a shirt-pocket device — a capability that ten years earlier would have required a dedicated spectrum analyser worth tens of thousands of dollars.
Third-party hardware expanded rapidly once the chip was cheap enough that improvement and cloning were commercially viable. The Pluto+ added 2×2 MIMO, a TCXO, and gigabit Ethernet. MicroPhase in Wuhan developed the ANTSDR series, pairing the AD9361 or AD9363 with a larger Zynq FPGA and running interchangeably as a PlutoSDR or USRP-compatible device. The ecosystem that formed around a $40 chip now spans continents and underpins research from EW waveform development at defence universities to ionospheric monitoring, passive radar prototyping, and GNSS anti-spoofing research. The AD936x did not merely sell well; it established a new floor for what accessible RF hardware means, from which every subsequent generation of researcher — and every subsequent generation of chip — departs.
SDR2026 welcomes presentations that explore any dimension of this arc: the ADC design trade-offs that made integrated direct-conversion transceivers viable; the VCO ADC and direct-RF-sampling research pushing the next frontier; the AD936x ecosystem in EW training, passive radar, open cellular, and amateur satellite applications; and comparative assessments of the AD936x against successor platforms including the ADRV9009 and the emerging generation of RF-sampling converters. Australian and New Zealand contributions — from DST Group, the universities, and the amateur community — are particularly encouraged.
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