A Field Programmable Gate Array is a semiconductor device whose internal logic, interconnect, and memory resources can be configured after manufacture to implement almost any digital circuit — and reconfigured again when requirements change. For software-defined radio, this is the defining capability. Where a general-purpose CPU processes samples sequentially, an FPGA implements deeply pipelined parallel logic with deterministic, jitter-free timing: polyphase filter banks, FFT engines, digital down-converters, correlators, beamformers, and protocol-specific demodulators execute simultaneously as dedicated hardware structures, not competing threads. Workloads that would saturate a multi-core CPU become a structured silicon pipeline that consumes the available sample stream with no dropped data. That combination of throughput, latency determinism, and reconfigurability has made FPGAs the processing backbone of serious SDR platforms across the full range from student experimentation to sovereign defence systems — and the trajectory of the technology is accelerating rather than levelling off.
The Platform Landscape — From USRP to RFSoC
Ettus Research established the reference architecture with the USRP line, and the progression of FPGA silicon inside successive generations maps the industry’s growth directly. The N200 and N210 used a Xilinx Spartan-6; the X300 and X310 stepped up to Kintex-7; the current flagship X410 — built on the Xilinx Zynq Ultrascale+ ZU28DR RF System-on-Chip — delivers four independent transmit and receive channels each capable of 400 MHz instantaneous bandwidth from 1 MHz to 7.2 GHz. The X410 is also the platform on which Ettus ships its RF Network-on-Chip (RFNoC) framework: a modular FPGA architecture in which signal processing functions are implemented as “NoC Blocks” connected via a crossbar, with a GNU Radio interface that makes custom FPGA acceleration accessible without requiring expertise in full chip integration. The entire UHD driver stack and the FPGA HDL are published under LGPL on GitHub, making the USRP ecosystem the most comprehensively open professional SDR platform available.
Lime Microsystems took a different path. The original LimeSDR paired the LMS7002M transceiver with a Xilinx Artix-7 in a full-size USB board; the LimeSDR Mini reduced this to an Intel MAX10, later redesigned as the Mini 2.0 with a Lattice ECP5 — a deliberate choice that enables a fully open-source FPGA toolchain via Yosys and nextpnr without any proprietary synthesis licence. The LimeSDR Micro, announced in 2025, adds an M.2 form factor and a vector accelerator. The LimeSDR FPGA gateware repository (LimeSDR_GW) now unifies the design across variants using the LiteX SoC framework. Nuand’s bladeRF 2.0 micro pairs a Cyclone V with the AD9361 transceiver in a compact USB form; Analog Devices’ ADALM-PLUTO uses the Zynq-7010 to run Linux and real-time FPGA processing below $200 — the platform that brought genuine FPGA-backed SDR into university teaching labs worldwide. For compact, SWaP-constrained deployments, Epiq Solutions’ Sidekiq Z2 packages a complete Zynq-based SDR into an M.2 card weighing eight grams and drawing under 2 W, targeted at UAS payloads and embedded RF intelligence. At the wideband professional end, Per Vices’ Chestnut uses an Intel Stratix 10 SoC to deliver up to 500 MHz bandwidth per chain across four coherent channels from near-DC to 9 GHz; their Calamine extends that range to 40 GHz for wideband EW monitoring. Pentek’s Onyx family pairs Xilinx Virtex FPGAs with high-speed ADC/DAC front ends in VPX and PCIe form factors for rackmount defence and instrumentation applications.
RFSoC — The Architecture That Changed the Frontier
The most significant shift in FPGA-based SDR over the past five years has not been in programmable logic density but in where the data converters sit. Xilinx’s Zynq Ultrascale+ RFSoC family — now produced under the AMD brand — placed multi-gigasample ADCs and DACs directly on the same die as the programmable logic, eliminating the high-speed serial interface between converter and FPGA that had been both a design challenge and a source of latency in every previous generation of platform. The first-generation RFSoC devices offered eight 12-bit ADCs at 4.096 GSPS and eight 14-bit DACs at 6.554 GSPS, providing up to 2 GHz of instantaneous bandwidth and covering sub-6 GHz 5G bands through direct RF sampling or harmonic mixing. The ZCU111 evaluation kit made these devices accessible to university research groups and the platform quickly attracted an academic ecosystem. The University of Strathclyde’s StrathSDR group, led by Robert Stewart and Louise Crockett, built the RFSoC-PYNQ open-source framework around it: Jupyter notebooks, Python overlays, and pre-built bitfiles that allow researchers to prototype spectrum analysers, OFDM transceivers, and modulation classifiers without writing a line of HDL. In 2025, the Strathclyde group published an FPGA-based convolutional neural network for streaming modulation classification operating in real time on the RFSoC2x2 — the kind of AI/RF integration that previously required a GPU cluster.
AMD extended the RFSoC line further with Gen 3 devices including the ZU47DR and ZU49DR, reaching higher bandwidth and channel count. Then in December 2024 AMD announced the Versal RF Series: adaptive SoCs combining the AI Engine array and programmable logic of the Versal architecture with 14-bit RF-ADCs and RF-DACs operating directly to 18 GHz. The RF-DAC samples at up to 16 GSPS; two ADC configurations are offered at 8 GSPS and 32 GSPS respectively. Chip-integrated hard IP blocks include 4 GSPS FFT/iFFT engines, a channeliser, and an LDPC decoder supporting DVB-S2x codes, alongside 80 TOPS of DSP throughput. Evaluation kits are planned for Q4 2025. The Versal RF Series is explicitly targeted at 6G research, phased-array radar, aerospace, and test-and-measurement — but the architectural principle it embodies — that the ADC, the FPGA, and an AI compute engine belong on the same die — is reshaping what researchers expect from the next generation of SDR platforms.
Open-Source Frameworks — RFNoC, Maia SDR, and OpenCPI
The commercial hardware story is inseparable from the open-source software and gateware ecosystem that makes it usable. RFNoC (RF Network-on-Chip) is the framework developed by Ettus Research and NI that exposes USRP FPGA resources through a standardised block interface compatible with GNU Radio. A user designs a custom signal processing block in Verilog or VHDL, wraps it as a NoC Block, and connects it to GNU Radio flowgraphs through the gr-ettus out-of-tree module — without restructuring the host application or the FPGA infrastructure. GNU Radio Conference 2025 (GRCon25) featured a dedicated RFNoC workshop covering the full development cycle. FPGA partial reconfiguration, which allows subsections of an FPGA design to be swapped at runtime without interrupting the remainder of the signal chain, is an active area in the RFNoC roadmap and is directly applicable to cognitive radio and waveform-agile EW systems where the radio must adapt its processing chain on the fly.
Maia SDR, the open-source firmware for the ADALM-PLUTO written by Daniel Estévez (EA4GPZ), represents a different philosophy: rather than wrapping an existing platform API, it replaces the entire FPGA gateware and ARM software stack with a design implemented in Amaranth HDL (a Python-based hardware description language) and Rust, delivering a real-time 61.44 Msps wideband waterfall and SigMF IQ recorder accessible through any WebGL2-capable browser. Presented at FOSDEM 2024, Maia SDR demonstrates that a skilled individual working in modern open HDL tooling can produce professional-grade SDR capability on a $200 platform. The LimeSDR gateware project pursues the same principle — unified open gateware for all LimeSDR variants using the LiteDRAM and LiteEth SoC components — and the LimeSDR Mini 2.0’s use of a Lattice ECP5 ensures the entire flow from synthesis to bitfile requires no vendor licence at all.
OpenCPI (Open Component Portability Infrastructure) is the framework most closely associated with defence-grade FPGA SDR. Originally developed with US Department of Defense funding and now maintained as an open-source project, OpenCPI defines component-based workers in VHDL, Verilog, or C/C++ that execute on heterogeneous targets — FPGA fabric, ARM processors, and GPUs — through a common runtime API. The framework is used extensively in US DoD SDR programmes where portability across hardware generations and export-control considerations matter. Its presence in the defence SDR ecosystem is extensive; adoption outside classified programmes is growing but less visible in the open literature.
Defence and EW — Reconfigurability as a Strategic Asset
For electronic warfare the core value proposition of an FPGA is not merely performance — it is in-field adaptability. A threat emitter whose signature is learned in the field this week can be countered by a new detection or jamming waveform pushed to deployed hardware this month, without returning the platform to depot. Dynamic partial reconfiguration allows sections of the FPGA design to be swapped at runtime — a jammer waveform can be replaced with a deception modulator while the ESM receiver continues operating uninterrupted. The US Air Force Research Laboratory’s Adaptive Waveform Generation for Extreme RF (AWGER) programme explicitly targets cognitive radio techniques that autonomously select waveform and frequency based on spectral sensing, a task for which FPGA-based SDR is architecturally suited. At the commercial-military interface, platforms like Per Vices’ Chestnut and Crimson, Pentek’s VPX-format Onyx boards, and CesiumAstro’s space-qualified SDR-1001 — which provides an open FPGA development kit for customer-defined waveforms across L- through Ka-band — give defence integrators COTS-grade building blocks with reconfigurability as a first-class feature rather than an afterthought.
In Australia, DEWC Systems — which rebranded as Asension in 2024 — is a South Australian company developing software-definable EW systems for space, air, sea, and land deployment, with remote reconfiguration designed in from the outset. The WOMBAT platform, originally built for space domain awareness, demonstrates that reconfigurable FPGA-based EW hardware can be designed and manufactured domestically in South Australia. Silentium Defence’s Oculus system for resident-space-object cataloguing, and Daronmont Technologies’ passive coherent location systems, both embed FPGA signal processing as the engine behind their detection algorithms. DST Group at RAAF Edinburgh remains the primary government research body coordinating sovereign reconfigurable hardware capability across the services, and its partnerships with all 32 Australian universities mean that FPGA-based SDR research conducted in academic labs regularly feeds directly into defence programme requirements.
Australian and New Zealand Research Activity
The Australian SDR and FPGA research community is more active than the published literature alone suggests. The most visible recent programme is the collaboration between Adelaide-based Inovor Technologies and the Australian National University (ANU), funded through the $180-million iLAuNCH space manufacturing initiative, to co-develop a resilient software-defined radio for space-to-ground and inter-satellite links. ANU provides simulation models and validates design choices; Inovor produces the prototype hardware and will integrate the SDR into its Apogee satellite bus for on-orbit demonstration. The design requirements — radiation tolerance, autonomous frequency and waveform adaptation, and high data-rate links — map directly onto the kind of FPGA-centric reconfigurable architecture that the broader SDR community has been developing in terrestrial applications. Inovor’s track record of building and operating Australia’s first domestically manufactured satellites gives the programme credibility beyond the research stage.
At the Australian GNU Radio Days 2025, held at the Festival Tower campus of Flinders University in September, presentations included FPGA-accelerated ADS-B Doppler detection — an undergraduate project implementing carrier frequency estimation on FPGA within an SDR chain — and Allan deviation measurement for SDR oscillator characterisation. The event reflected a healthy pipeline of student and researcher engagement with FPGA-based SDR across South Australian institutions. The University of Adelaide’s Buckland Park atmospheric radar facility provides a local example of research-grade reconfigurable signal processing at HF and VHF, while UNSW Canberra’s long-running radio and EW research connects academic FPGA work directly to ADF capability development. Across the Tasman, the University of Auckland and Victoria University of Wellington have both engaged with RFSoC platforms through AMD’s academic programme, and KiwiSDR — designed and built in New Zealand by John Seamons — remains the most widely deployed HF SDR instrument on earth, with over 700 active public receivers, even if its FPGA (a Xilinx Zynq Z-7010) operates in a supporting role behind the broadband ADC front end.
SDR2026 welcomes presentations on every dimension of FPGA and reconfigurable hardware in SDR: RFSoC and Versal RF platform results from research groups; open-source gateware projects including Maia SDR, RFNoC custom blocks, and LimeSDR gateware contributions; OpenCPI and other framework-based development for portable SDR applications; dynamic partial reconfiguration for cognitive radio and EW; FPGA implementation of AI/ML inference for real-time signal classification; beamforming and multi-channel coherent SDR; Australian and New Zealand design wins including the Inovor/ANU space SDR and sovereign EW platform developments; and comparative assessments of synthesis toolchains from Vivado and Quartus through to fully open flows using Yosys and nextpnr. Papers from university groups at any career stage, and from defence industry and amateur experimenters, are equally encouraged. If you have built custom HDL for a radio application — on any fabric, at any scale — this is where it belongs.